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AS 1.1.1 - Structure and Function of the Processor


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Central Processing Unit
the part of a computer in which operations are controlled and executed
Control Unit
controls and coordinates the activities of the CPU, directs the flow of data between the CPU and other devices, and manages the Fetch-Decode-Execute cycle
Bus
a set of parallel wires which connect two or more components of a computer; usually 8, 16, 32 or 64 lines
System Bus
the data, address and control bus collectively; they connect the CPU, main memory and I/O controllers; only one device can transmit along a bus at any one time
Address Bus
part of the system bus, the CPU sends the address of the location they want to access to memory on this bus; signals travel only from the CPU to memory or I/O controller, it is a unidirectional bus
Data Bus
part of the system bus, moves data and instructions between system components, according to the specified memory location; it is a bidirectional bus
Control Bus
part of the system bus, transmits command, timing and specific status information between system components, making sure that the use of the data and address busses by different system components does not lead to conflict; it is a bidirectional bus
Bus Request
Control Line: indicates that a device is requesting the use of the data bus
Bus Grant
Control Line: indicates that the CPU has granted access to the data bus
Memory Write
Control Line: causes data on the data bus to be written into the addressed location
Memory Read
Control Line: causes data from the addressed memory location to be placed on the data bus
Interrupt Request
Control Line: indicates that a device is requesting access to the CPU
Clock
Control Line: used to synchronise operations
word
a fixed size group of digits which is handled as a unit by the processor (often 16, 32 or 64 bits, although it varies in different processors); these units are made from memory being divided internally and have their own location address
Arithmetic Logic Unit
part of the CPU which performs arithmetic and logical operations on data; such as mathematical operators, shift operations and boolean logic operations
registers
special memory cells that operate at very high speeds, where all arithmetic, logical or shift operations take place
16
There are typically up to how many general purpose registers in the CPU?
accumulator
a register for short-term, intermediate storage of arithmetic and logic data in a computer's CPU (associated with the ALU)
program counter
holds the address of the next instruction to be executed. This could be the next instruction in a sequence or if the current instruction is a branch or jump instruction, the address to jump to (which is copied from the CIR)
current instruction register
holds the current instruction being executed, divided into operand and opcode
memory address register
holds the address of the memory location from which data or an instruction is to be fetched or to which data is to be written
memory data register
used to temporarily store the data read from or written to memory. It is sometimes known as the memory buffer register as it acts like a buffer, temporarily storing data before passing it on
fetch-decode-execute
the basic steps / cycle that a CPU carries out to process and execute an instruction
MAR
FETCH (1): the address of the next instruction is copied from the PC to the...
incremented
FETCH (2): the instruction at that address is copied to the MDR, while the content of the PC is simultaneously ... so that it holds the address of the next instruction
CIR
FETCH (3): the contents of the MDR are copied to the ...
decoded
DECODE (4): the instruction in the CIR is ... and split into an opcode and operand
ALU
EXECUTE (5): the appropriate instruction / opcode is carried out on the operand in the ...
opcode
the portion of a machine language instruction that specifies the operation to be performed / the type of instruction, as well as what hardware to use to execute it
operand
the part of a computer instruction that specifies the address of the data to be used with the operation (thus copied to the MAR) or the actual data to be operated on (thus copied to the MDR and may be passed to the ALU)
clock speed
Factor affecting CPU Performance: the operating speed of a computer or its microprocessor, measured in Gigaherz (the faster this is, the faster instructions will be executed)
system clock
a device in a computer that generates a series of signals, switching between 0 and 1 several million times a second, synchronising CPU operations, as each operation starts when the clock changes from 0 to 1
clock cycle
the time it takes the system clock to go from 0 to 1 and back to 0; operations cannot be carried out faster than this, but some can take more than one of these to complete
1 Hz
one clock cycle per second =
number of cores
Factor affecting CPU Performance: each core can process a different instruction at the same time, making the processor faster with multiple cores
dual-core processor
two processors linked together in the same integrated circuit
quad-core processor
four processors linked together in the same integrated circuit
both processors
Although a dual-core processor has twice the power of a single core, it may not always perform twice as fast, as some software cannot always take full advantage of...
Cache Memory
extremely fast storage medium, closer to the processor than the main memory, which holds frequently accessed code and data, although has a very small capacity; is expensive
memory
when an instruction is fetched from main memory, it is copied into the cache so that it can be fetched from the cache if it is needed again soon after, as this is quicker than retrieving it again from main ...
replaced
when the cache fills up, more recent instructions will cause unused instructions that are still being stored there, to be ...
Level 1 Cache
cache which is directly built into the microprocessor and is the primary cache as it is extremely fast but there is only a small amount of it in the processor (2-64KB)
Level 2 Cache
cache which is outside the processor chip core, but is closer than Level 3 cache; it is fairly fast and there is a medium sized amount of it (256KB - 2MB)
Level 3 Cache
cache which is usually built onto the motherboard and is slower than Level 2 cache, but faster than main memory
memory capacity
the width of the address bus (the number of lines it has) determines the system's maximum possible...
word size
the largest operand that can be held in a word is determined by the size of the data bus; this is also known as the ...
smaller word size
computers with a larger word size may perform more quickly than computers with a ...
von Neumann architecture
specifies the basic components of the computer and processor, where a shared bus and memory is used for both data and instructions
stored program concept
the idea that a program is electronically stored as binary in memory (RAM) so that it can be modified
same word size
In von Neumann machines, one data bus and address bus is used for both data and instructions and so regardless of whether the bus holds data or instructions, the ... is used
general purpose
Von Neumann architecture is primarily used in ... computer systems
Harvard architecture
computer architecture with physically separate memory for data and for instructions
Digital Signal Processing systems
refers to systems that employ various techniques for improving the accuracy and reliability of digital signals; applications include audio & speech signal processing, sonar & radar signal processing, biomedical signal processing, seismic data processing and digital image processing
DSP
Harvard architecture is used extensively with embedded ... systems
embedded systems
special-purpose computer systems built into larger mechanical systems / other devices (often running in real time), such as navigation systems, traffic lights, aircraft flight control systems and simulators
optimised in size
Advantage of Von Neumann: programs can be ...
design and development
Advantage of Von Neumann: simplifies the ... of the control unit
flexible
Advantage of Von Neumann: more ..., as the storage needed for instructions and for data doesn't have to be decided ahead of time
implemented
Disadvantage of Von Neumann: pipelining cannot be...
program error
Disadvantage of Von Neumann: instructions could be accidentally rewritten by a ...
in parallel
Advantage of Harvard: pipelining can be used, meaning it can be faster than Von Neumann as data and instructions can be fetched ...
characteristics
Advantage of Harvard: the data memory and instruction memory can have different ... (e.g. instruction memory be read-only, and data memory be read-write)
instruction memory
Advantage of Harvard: different word sizes / bus widths can be used for each memory section, which is good as in systems, there is often more ...
larger
Disadvantage of Harvard: programs tend to be ...
costly
Disadvantage of Harvard: a CPU with two sets of busses makes its production require more time and be more ...
Von Neumann bottleneck
when instructions can’t be fetched at the same time as data is being sent along the bus, meaning the CPU has to wait for each item to be fetched and executed individually, limiting the performance of the processor
modern high-performance CPU chips
incorporate aspects of both Von Neumann and Harvard architectures
Modified Harvard
a contemporary processor architecture where separation of the data and instructions is done through separate caches utilising the same memory space