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A2 1.1.1 - Structure and Function of the Processor


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pipelining
technique to improve processor performance: while one instruction is being fetched, another is being decoded, and another is being executed
inefficient
without pipelining, parts of the CPU will be idle while other stages of the Fetch-Decode-Execute cycle are carried out, which is ...
in a buffer
instructions that are fetched while the processor performs other operations, are stored ...
arithmetic pipeline
processor pipelining can be divided into an instruction pipeline and an ...
instruction pipeline
the pipeline for the Fetch-Decode Execute cycle
performed
an arithmetic pipeline is the pipeline for parts of arithmetic operations that can be broken down and overlapped as they are ...
stages
a pipeline can have many ...
pipeline stall
when parts of the CPU remain dormant as they wait for other parts to finish processing an instruction whose result is needed for the next one
hyper threading
when the CPU is able to fill pipeline bubbles with other non-dependent instructions from different threads
flushing
this process is required when a jump instruction causes the program counter to change (and so the pipeline needs to be reset)
superscalar processor
a processor able to execute multiple instructions simultaneously on one core